1. Field of the Invention
The present invention relates to memory circuits (e.g., flash memory chips or other integrated nonvolatile memory circuits) which include a state machine for controlling performance of memory operations, and to methods of operating such a state machine to generate control signals (for controlling performance of such memory operations). In preferred embodiments, the inventive memory chip includes a state machine which includes a controllable (reconfigurable) one-shot circuit for asserting a control signal (with controllable duration) in response to a trigger signal.
2. Description of Related Art
Throughout the specification, including in the claims, the term "connected" is used (in the context of an electronic component being "connected" to another electronic component) in a broad sense to denote that the components are electrically or electromagnetically coupled with sufficient strength under the circumstances. It is not used in a narrow sense requiring that an electrically conducting element is physically connected between the two components.
Nonvolatile memory chips (integrated circuits) are becoming increasingly commercially important. A typical nonvolatile memory chip includes an array of nonvolatile memory cells, each cell comprising a transistor having a floating gate capable of semipermanent charge storage. The current drawn by each cell depends on the amount of charge stored on the corresponding floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell.
One particularly useful type of nonvolatile memory chip includes an array of flash memory cells, with each cell comprising a flash memory device (a transistor). The charge stored on the floating gate of each flash memory device (and thus the data value stored by each cell) is erasable by appropriately changing the voltage applied to the gate and source (in a well known manner).
FIG. 1 is a simplified block diagram of a conventional nonvolatile memory chip. Integrated circuit 3 of FIG. 1 includes at least one I/O pad 30 (for asserting output data to an external device or receiving input data from an external device), input/output buffer circuit 10 for I/O pad 30, address buffers AO through Ap for receiving memory address bits from an external device, row decoder circuit (X address decoder) 12, column multiplexer circuit (Y multiplexer) 14, and memory array 16 (comprising columns of nonvolatile memory cells, such as column 16A). Each of address buffers AO through Ap includes an address bit pad for receiving (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym.
I/O buffer circuit 10 includes a "write" branch and a "read" branch. The write branch comprises input buffer 18. The read branch comprises sense amplifier 19 and output buffer 20. Chip 3 executes a write operation by receiving data (to be written to memory array 16) from an external device at I/O pad 30, buffering the data in the write branch, and then writing the data to the appropriate memory cell. Chip 3 can also be controlled to execute a read operation in which it amplifies and buffers data (that has been read from array 16) in the read branch, and then assert this data to I/O pad 30.
Although only one I/O pad (pad 30) is shown in FIG. 1, typical implementations of the FIG. 1 circuit include a plurality of I/O pads, and each I/O pad is buffered by an I/O buffer circuit similar or identical to circuit 10. For example, one implementation of the FIG. 1 circuit includes eight I/O pads, eight buffer circuits identical to circuit 10, one line connected between the output of the output buffer 20 of each buffer circuit and one of the I/O pads (so that eight data bits can be read in parallel from buffers 20 to the pads), and one line connected between the input of the input buffer 18 of each buffer circuit and one of the I/O pads (so that eight data bits can be written in parallel from the pads to buffers 18). Each I/O pad (including I/O pad 30) typically has high impedance when the output buffer is not enabled.
Each of the cells (storage locations) of memory array circuit 16 is indexed by a row index (an "X" index determined by decoder circuit 12) and a column index (a "Y" index output determined by decoder circuit 14). Each column of cells of memory array 16 (e.g., column 16A of FIG. 1) preferably comprises "n" memory cells, each cell implemented by a floating-gate N-channel transistor. The drain of each transistor is connected to a common bitline, and the gate of each is connected to a different wordline. The source of each of transistor is held at a source potential (which is usually ground potential for the chip during a read or programming operation).
In the case that each memory cell is a nonvolatile memory cell, each of the transistors has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of the transistors) depends on the amount of charge stored on the corresponding floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell.
In response to address bits Y0-Ym, circuit 14 (of FIG. 1) determines a column address which selects one of the columns of memory cells of array 16 (connecting the bitline of the selected column to Node 1 of FIG. 1), and in response to address bits X0-Xn, circuit 12 (of FIG. 1) determines a row address which selects one cell in the selected column. To read the data value stored in the selected cell, a signal (a current signal) indicative of such value is provided from the cell's drain, through the cell's bitline and circuit 14, to node 1 of FIG. 1. To write a data value to the selected cell, a signal indicative of such value is provided to the cell's gate and drain.
More specifically, the FIG. 1 circuit executes a write operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to decoder circuit 12, and each of address buffers An+l through Ap asserts one of bits Y0-Ym to multiplexer circuit 14. In response to these address bits, circuit 14 determines a column address (which selects one of the columns of memory cells of array 16, such as column 16A), and circuit 12 determines a row address (which selects one cell in the selected column). In response to a write command (which can be supplied from control unit 29, or other circuitry to be described below), a signal (indicative of data) present at the output of input buffer 18 is asserted through circuit 14 to the cell of array 16 determined by the row and column address (e.g., to the drain of such cell). During such write operation, output buffer 20 may be disabled. A data latch (not shown) is typically provided between input buffer 18 and I/O pad 30 for storing data (to be written to a memory cell) received from I/O pad 30. When the latched data is sent to input buffer 18, input buffer 18 produces a voltage at Node 1 which is applied to the selected memory cell. Input buffer 18 is typically implemented as a tri-statable driver having an output which can be placed in a high impedance mode (and thus disabled) during a read operation. In some implementations, the functions of the latch and input buffer 18 are combined into a single device.
The FIG. 1 circuit executes a read operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to address decoder circuit 12, and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to address decoder circuit 14. In response to these address bits, circuit 14 asserts a column address to memory array 16 (which selects one of the columns of memory cells, such as column 16A), and circuit 12 asserts a row address to memory array 16 (which selects one cell in the selected column). In response to a read command (supplied from control unit 29, or from other circuitry to be described below), a current signal indicative of a data value stored in the cell of array 16 (a "data signal") determined by the row and column address is supplied from the drain of the selected cell through the bitline of the selected cell and then through circuit 14 to sense amplifier 19. This data signal is processed in amplifier 19 (in a manner to be described below), and the output of amplifier 19 is buffered in output buffer 20 and finally asserted at I/O pad 30.
When reading a selected cell of array 16, if the cell is in an erased state, the cell will conduct a first current which is converted to a first voltage in sense amplifier 19. If the cell is in a programmed state, it will conduct a second current which is converted to a second voltage in sense amplifier 19. Sense amplifier 19 determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary value of 1 or 0, respectively) by comparing the voltage indicative of the cell state to a reference voltage. The outcome of this comparison is an output which is either high or low (corresponding to a digital value of one or zero) which sense amplifier 19 sends to output buffer 20, which in turn asserts a corresponding data signal to I/O pad 30 (from which it can accessed by an external device.
Nonvolatile memory chip 3 of FIG. 1 can also execute an erase operation in which all or selected ones of the cells of memory array 16 are erased in response to a sequence of one or more commands (e.g., an "Erase Setup" command followed by an "Erase Confirm" command)), by discharging a quantity of charge stored on the floating gate of each cell. Typically, all cells of array 16 or large blocks of such cells are erased at the same or substantially the same time during an erase operation. Each erase operation comprises a sequence of steps, including "verification" steps for verifying that the cells have desired threshold voltages at each of one or more stages of the erase operation. A verification step is also typically performed during a cell programming operation (in which a cell is programmed to have a threshold voltage different from the threshold voltage of an erased cell), to determine whether the cell has been programmed to have the desired threshold voltage.
More specifically, if cells of memory array 16 of FIG. 1 are to be erased, an "Erase Setup" command and then an "Erase Confirm" command are sent from an external device to I/O pad 30. Where each such command comprises parallel bits, the different bits are sent in parallel to I/O pad 30 and to additional I/O pads identical to I/O pad 30. The command is transferred from I/O pad 30 (or from I/O pad 30 and additional I/O pads) to input buffer 18 (or input buffer 18 and input buffers connected to the other I/O pads), and then to control unit 29. Control unit 29, which typically includes command execution logic and a state machine, processes each command to generate instruction data, and supplies the instruction data to circuit 14 and sense amplifier 19 (and to other components of memory chip 3 of FIG. 1) to cause chip 3 to execute a sequence of steps required for erasing the specified cells of array 16. These steps include verification steps (e.g., the verification step discussed below) for verifying that the cells have desired threshold voltages at each of one or more stages of the erase operation.
During each verification step, verification data output from sense amplifier 19 is fed back to control unit 29. Typically, an external device polls output pads of chip 3 in order to determine whether the erase operation has been completed and whether the erase operation was successful.
A conventional memory erase operation is next described in greater detail with reference to FIG. 2. FIG. 2 is a block diagram of a conventional flash memory system 103 which is a variation on memory chip 3 of FIG. 1 which performs essentially all the same functions as does chip 3. The components of flash memory system 103 which correspond to components of memory chip 3 of FIG. 1 are identified by the same reference numerals as in FIG. 1. Memory array 16 of system 103 consists of flash memory cells arranged in rows and columns with there being a total of 256K of eight bit words in the array. The individual cells (not depicted) are addressed by eighteen address bits (A0-A17), with nine bits being used by X decoder circuit 12 to select the row of array 16 in which the target cell is located and the remaining nine bits being used by Y decoder circuit 14A (of Y-multiplexer 14) to select the appropriate column of array 16.
Internal state machine 120 of memory system 103 controls detailed operations of system 103 such as the various individual steps necessary for carrying out programming, reading and erasing operations. Each of these primary operations is comprised of a large number of sub-operations. In addition, state machine 120 controls such operations as reading or clearing status register 126, identifying chip 103 in response to an identification command, and suspending an erase operation. State machine 120 functions to reduce the overhead required of the external processor (not depicted) typically used in association with chip 103.
A preferred implementation of a state machine for use as state machine 120 of FIG. 2 is described in U.S. Pat. No. 5,629,644, issued on May 13, 1997. This preferred state machine implementation (shown in FIG. 3) includes a single circuit which controls several different memory operations (e.g., programming and erasing operations) and sub-operations, where at least one of the sub-operations is common to two or more of the memory operations. As shown in FIG. 3, the state machine includes sequencer module 210 which operates in response to high level operation command signals (such as signals 211 and 212) generated by a device external to chip 103. Each command signal is typically an instruction to carry out a block erase operation on the memory cells of an array or a programming operation on a specified memory cell.
Command signals 211 and 212 cause sequencer 210 to produce output signals which control the operation of loop controller module 220, timer module 230, pulse counter module 240, and address counter module 250. These modules are used to execute the erase or programming operation by controlling the order and manner in which various sub-operations used in those operations are performed.
The outputs of sequencer 210 are control signals including a sequence start signal 215 that initiates loop controller circuit 220 and a control signal corresponding to the operation or sub-operation to be executed. These operations and sub-operations include internal programming operation 216, pre-programming operation 217, internal erase operation 218, and healing operation 219, where the pre-program, internal erase, and healing operations are part of an erase operation. The control signal(s) corresponding to the operation or sub-operation to be executed are also provided to timer module 230, pulse counter module 240, and address counter module 250.
Loop controller 220 is activated by sequence start signal 215 issued by sequencer 210. Loop controller 220 contains circuitry which responds to the sequence start signal and the control signal (e.g., 216, 217, 218, or 219) indicating which operation or sub-operation is to be executed, by generating the control signals 222 needed to cause the high voltage pulse generator circuits to produce a desired voltage pulse for programming or erasing a cell. Loop controller 220 also generates control signals 223 as needed for controlling the chip's sense amplifiers (e.g., those within unit 100 of FIG. 2) during the indicated operation or sub-operation.
Timer module 230 contains circuitry which produces an output pulse of variable duration. A description of timing circuitry suitable for use in timer module 230 is found in U.S. patent application Ser. No. 08/509,035, entitled "Adjustable Timer Circuit", filed on Jul. 28, 1995, which is incorporated herein in full by reference. Timer module 230 receives start signal 226 from loop controller 220 which initiates the timing circuitry. Start signal 226 causes the timing circuitry to initiate a timing sequence of duration determined by which control signal (216, 217, 218, or 219) is active. At the conclusion of the specified time period, timer module 230 outputs an end signal 227 to loop controller 220. End signal 227 causes loop controller 220 to terminate the operation or sub-operation whose execution it is controlling, and initiate a new operation.
The control signals output by sequencer 210 are also provided to pulse counter module 240. Pulse counter module 240 also receives increment pulse counter signal 225 from loop controller 220. The control signals from sequencer 210 set pulse counter 240 to the appropriate value based on the operation or sub-operation to be executed. During execution of the operation or sub-operation, loop controller 220 outputs "Increment Pulse Counter" signal 225 as required in accordance with the stage of execution of an operation. When the maximum pulse counter value (determined by the input signal(s) from sequencer 210) has been reached, pulse counter module 240 outputs a maximum pulse counter signal 228 which is used to terminate a program or erase operation.
Reset signal 261 is provided to all elements of state 120. Maximum pulse counter signal 228 can trigger assertion of reset signal 261, which will end the operation being executed (e.g., to prevent endless cycling of the state machine through the operation).
The control signals output by sequencer 210 are also provided to address counter module 250, and module 250 also receives increment address counter signal 224 from loop controller 220. The control signals from sequencer 210 set the address counter to the appropriate value based on the operation or sub-operation to be executed. Address counter module 250 includes an address counter/incrementer module and a combinational logic module which operate to produce the memory cell addresses output on address bus 231 and maximum address ("MaxAdd") signal 229. During execution of an operation or sub-operation, loop controller 220 outputs "increment address counter" signal 224 as required in accordance with the stage of execution of the operation (or sub-operation). When the maximum address counter value (determined by the input signal or signals received at module 250 from sequencer 210) has been reached, address counter module 250 asserts maximum address signal 229 to loop control module 220 and sequencer 210 to indicate that the operation or sub-operation has been completed.
Another use of the increment pulse counter signal and increment address counter signal is as part of a control scheme for terminating an operation. By appropriately setting the maximum address and pulse counter values, the increment counter signals can be used to increment the counters to those maximum values after a single cycle (or any desired number of cycles). This allows execution of only part of the sequence of operations that would normally occur, and is part of the control scheme that allows using the same functional modules for executing the high level operations.
With reference again to FIG. 2, if memory array 16 is to be erased (typically, all or large blocks of cells are erased at the same time), an external processor causes the Output Enable OE pin to be inactive (high) and the Chip Enable CE and Write Enable WE pins to be active (low). The processor can then issue an 8 bit command 20H (0010 0000) on data I/O pins DQ0-DQ7, typically called an Erase Setup command (one of I/O pins DQ0-DQ7 corresponds to I/O pad 30 of FIG. 1). This is followed by issuance of a second eight bit command DOH (1101 0000), typically called an Erase Confirm command. Two separate commands are used so as to minimize the possibility of an inadvertent erase operation.
The commands are transferred to data input buffer 122 (input buffer 18 of FIG. 1 corresponds to a component of buffer 122 which receives one bit of each command) and the commands are then transferred to command execution logic unit 124. Logic unit 124 then instructs state machine 120 to control chip 103's performance of a sequence of steps for erasing array 16. Once the erase sequence is completed, state machine 120 updates 8-bit status register 126, the contents of which are transferred to data output buffer 128 which is connected to data I/O pins DQ0-DQ7 of chip 103 (output buffer 18 of FIG. 1 corresponds to a component of buffer 128 which receives one bit from register 126). The processor periodically polls the data I/O pins to read the contents of status register 126 in order to determine whether the erase sequence has been completed and whether it has been completed successfully.
U.S. patent application Ser. No. 08/507,160 (filed on Jul. 26, 1995 and assigned to the assignee of the present application) describes in detail a typical erase sequence as it is carried out by state machine 120.
During any erase operation, it is possible that one or more cells of array 16 will become "overerased" in the sense that the net charge on the floating gate of each such cell becomes positive and the threshold voltage of each such cell becomes negative. When the word line connected to an overerased deselected cell is grounded, the deselected cell will nevertheless conduct current. This current will interfere with the reading of the selected cell thereby preventing proper memory operation. A principal objective of a preferred erase sequence controlled by state machine 120 is to erase all the cells of array 16 so that their threshold voltages are all within a specified voltage range, to avoid overerasing cells. The voltage range is typically a small positive voltage range such as +1.5 to +3.0 volts. If the erased cells fall within this range, the cell to be read (the "selected" or "target") cell will produce a cell current in a read operation. The presence of cell current flow indicates that the cell is in an erased state (logic "1") rather than a programmed state (logic "0"). Cell current is produced in an erased cell because the voltage applied to the control gate of the cell, by way of the word line from the array connected to X decoder 12, exceeds the threshold voltage of the erased cell by a substantial amount. In addition, cells which are not being read ("deselected" cells) are prevented from producing a cell current even if such cells have been erased to a low threshold voltage state. By way of example, cells located in the same row as the selected cell share the same word line as the selected cell. However, the drains of the deselected cells will be floating thereby preventing a cell current from being generated. Deselected cells in the same column will not conduct cell current because the word lines of such deselected cells are typically grounded. Thus, the gate-source voltage of these cells will be insufficient to turn on these deselected cells even if they are in an erased state.
Once array 16 has been erased, the vast majority of its cells will have a proper erased threshold voltage. However, it is possible that a few (or even one) of the cells may have responded differently to the erase sequence and such cell(s) have become overerased.
In a preferred erase sequence controlled by state machine 120, when the two above-mentioned erase commands have been received by command execution logic 124 (shown in FIG. 2), state machine 120 first causes all cells of array 16 to be programmed. This is done so that all cells are in essentially the same condition when they are subsequently erased. This reduces the likelihood that one or more of the cells will become overerased since all of the cells will have an increased tendency to respond to the subsequent erase sequence in the same manner. Then, an address counter (address counter module 250 which is a portion of state machine 120 of FIG. 2) is initialized to the first address of the memory. Next, the voltages used for programming are set to the proper level (including by providing a high voltage Vpp from Vpp switch 121 of FIG. 2 to status register 126, X and Y decoders 12 and 14A, and other components of FIG. 2).
Once the voltages are set, pulse counter module 240 within state machine 120 is initialized. This module will keep track of the number of programming pulses that have been applied to the cells of the word (byte) being programmed. Next, a programming pulse is applied to the cells of the word located at the first address of the memory. The pulse counter is then incremented and a determination is made as to whether a predetermined maximum number of pulses have been applied to the cells. If that is the case, the cells are read to determine whether the cells have, in fact, been programmed (this is a "verification" operation). The verification operation is accomplished using sense amplifiers and associated components represented by block 100 of FIG. 2.
If the cells are still not programmed at this point, there has been a failure since he maximum number of programming pulses has been exceeded. Depending upon the particular memory, the sequence will be terminated or a record of the failed word will be made and the sequence continued. This information will then be transferred to status register 126 (FIG. 2) so that it can be read by an external processor.
Assuming that the maximum count has not been exceeded, the byte is verified. If the byte has not been programmed, a further programming pulse is applied and the counter is incremented. Assuming that the maximum count has still not been exceeded, the byte is again verified. This sequence continues until the byte finally passes the verification test or until the pulse counter is at the maximum.
Assuming that the first byte is eventually successfully programmed, a determination is made as to whether the last address of array 16 has been programmed. If that is not the case, address counter 250 (of FIG. 2) is incremented to the second address and the pulse counter reset. A first programming pulse is applied to the byte of the second address and the sequence is repeated. This process will continue until all cells of array 16 have either been programmed or until a determination is made that there is a programming failure.
Assuming that all of the cells have been successfully programmed and verified, state machine 120 will continue the erase sequence by setting the appropriate voltages used for erasing, including the initialization of the address counter 250 and the setup of the appropriate voltages for erasing, including voltage Vpp.
Next, the pulse counter is reset and a single erase pulse is applied to all of the cells of array 16 (or to the block of the array being erased in the event that capability is provided). The cells of array 16 will then be sequentially read (an "erase verification" test) in order to determine whether all cells have been successfully erased. A single erase pulse is almost never sufficient to accomplish an erasure so that the test on a first byte will almost always fail. The state of the pulse counter is then examined and a determination is made that the maximum count has not been exceeded. If it has not, a second erase pulse is applied to the entire array 16 and the first byte is again tested.
Once the byte has received a sufficient number of erase pulses and has passed the verification test, the address is incremented and a second byte is tested to determine whether the second byte has been successfully erased. Since the cells are not always uniform, it is possible that the second byte has not been erased even though it has received the same number of erase pulses received by the first byte. In that event, a further erase pulse is applied to the entire array 16 and the second byte is again tested for a proper erase.
Once it has been established that the second byte has been properly erased, a determination is made as to whether the last address of array 16 has been verified. If that is not the case, address counter 250 is incremented and a third byte is tested. Additional erase pulses will be applied if necessary. The pulse counter will monitor the total number of erase pulses applied in the erase sequence. If a maximum number has been exceeded, the sequence will be terminated and one of the bits of status register 126 will be set to reflect that an erase error has occurred.
Assuming that the second byte of cells has been properly erased, the remaining bytes will be verified and any necessary additional erase pulses will be applied. Once the last address has been verified, the erase sequence is ended and status register 126 is updated to indicate that the erase sequence has been successfully completed.
Before the present invention, state machines for controlling memory operations of a memory chip had used complicated timing circuits (e.g., timer module 230 of FIG. 3, including the complicated timing circuitry described in referenced U.S. patent application Ser. No. 08/509,035) to produce control signals with variable timing. For example, during different memory operations, the state machine of FIG. 3 controls timer 230 to assert end signal 227 at different times after assertion of start signal 226. Not only were such timing circuits complicated, but they typically operated to delay assertion of control signals for long time intervals (e.g., on the order of tens of milliseconds or one second), and were not capable of precisely controlling (e.g., to within a few tens of nanoseconds or even a few hundreds of nanoseconds) the delay interval preceding assertion of such a control signal.
Before the present invention, state machines for controlling memory operations of a memory chip had used one-shot circuits to assert control signals with short delay (e.g., tens or hundreds of nanoseconds). For example, loop control module 220 (shown in FIG. 3) of the state machine of referenced U.S. patent application Ser. No. 08/508,974 preferably includes several one-shot circuits, each for asserting a delayed control signal in response to an input control signal (or logical combination of input control signals). However, each such one-shot circuit had operated with a fixed delay between a trigger signal edge and the delayed output signal produced in response to the trigger signal edge (e.g., one such one-shot asserted an output pulse whose leading edge always occurred 500 nanoseconds after assertion of a trigger signal edge to the one-shot).
Until the present invention, state machines for controlling memory operations of a memory chip had not employed a simple but controllable one-shot circuit for asserting a delayed control signal with variable (and controllable) delay in response to a trigger signal edge.